Dram access transistor and method of formation

ABSTRACT

Self-aligned recessed gate structures and method of formation are disclosed. Field oxide area for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

FIELD OF THE INVENTION

The present invention relates to dynamic random access memory (DRAM)cells and, in particular, to a novel process for their formation.

BACKGROUND OF THE INVENTION

A dynamic random access memory cell typically comprises a charge storagecapacitor (or cell capacitor) coupled to an access device, such as aMetal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFETfunctions to apply or remove charge on the capacitor, thus affecting alogical state defined by the stored charge. The amount of charge storedon the capacitor is determined by the electrode (or storage node) areaand the interelectrode spacing. The conditions of DRAM operation such asoperating voltage, leakage rate and refresh rate, will generally mandatethat a certain minimum charge be stored by the capacitor.

In the continuing trend to higher memory capacity, the packing ofstorage cells must increase, yet each must maintain required capacitancelevels. This is a crucial demand of DRAM fabrication technologies.Recently, attempts to increase the packing density of cell capacitorsand/or to simultaneously reduce the transistor size have been made butwith limited results. For example, one approach is reducing the lengthof a transistor gate electrode formed atop a substrate and asource/drain region, to increase therefore the integration density.Unfortunately, reduction of the threshold voltage and/or the so-calledshort channel effect such as the punch-through phenomenon are likely toappear. A well-known scaling method is effective to improve theabove-mentioned disadvantages. However, this approach increases thesubstrate doping density and requires reduction of the supply voltage,which in turn leads to reduction of the margin concerning the electricnoise and fluctuations in the threshold voltage. Higher channel dopingcauses degradation in retention time due to high electric field at thestorage node junction.

Accordingly, there is a need for an improved method of forming MOSsemiconductor devices, which permits achieving an increased integrationof semiconductor circuitry as well as preventing the occurrence of theshort-channel effect without adding more dopants into the channel.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a method of formingmemory devices, such as DRAM access transistors, having self-alignedrecessed gate structures. A plurality of insulating columns are definedin an insulating layer formed over the semiconductor substratesubsequent to which a thin sacrificial oxide layer is formed overexposed regions of the semiconductor substrate. A dielectric material isthen provided on sidewalls of each column and over portions of thesacrificial oxide layer. A first etch is conducted to form a first setof trenches of a first width within the semiconductor substrate. As aresult of the first etch, the thin sacrificial oxide layer is completelyremoved, but the dielectric material is only partially removed formingdielectric residue on the sidewalls of the columns. A second etch isconducted to remove the dielectric residue remaining on the sidewalls ofthe columns and to form a second set of trenches of a second width whichis greater than the first width of the first set of trenches.

Another embodiment of the present invention provides a self-alignedrecessed gate structure for DRAM access transistors. The self-alignedrecessed gate structure comprises a first recessed gate region locatedbelow a surface of a semiconductor substrate and having a width of about35 nm to about 75 nm, more preferably of about 60 nm. The self-alignedrecessed gate structure also comprises a second gate region extendingabove the surface of said semiconductor substrate by about 20 nm toabout 800 nm. The second gate region has a width of about 50 nm to about100 nm, more preferably of about 80 nm. Insulating spacers are locatedon sidewalls of the second gate region but not on sidewalls of the firstrecessed gate region.

These and other advantages and features of the present invention will bemore apparent from the detailed description and the accompanyingdrawings, which illustrate exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic cross-sectional view of a portion of asemiconductor device on which a DRAM access transistor will be formedaccording to a method of the present invention.

FIG. 2 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 1.

FIG. 3 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 2.

FIG. 4 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 3.

FIG. 5 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 4.

FIG. 5 a illustrates a cross-sectional view of the FIG. 5 device takenalong line 5-5′.

FIG. 6 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 5.

FIG. 6 a illustrates a cross-sectional view of the FIG. 6 device takenalong line 6-6′.

FIG. 7 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 6.

FIG. 8 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 7.

FIG. 9 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 8.

FIG. 10 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 9.

FIG. 11 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 10.

FIG. 12 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 11.

FIG. 13 illustrates a cross-sectional view of the FIG. 1 device at astage of processing subsequent to that shown in FIG. 12.

FIG. 14 is an illustration of a computer system having a DRAM accesstransistor formed according to a method of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to variousspecific exemplary embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural, logical,and electrical changes may be made.

The terms “wafer” or “substrate” used in the following description mayinclude any semiconductor-based structure that has a semiconductorsurface. Wafer and structure must be understood to include silicon,silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor need not be silicon-based. The semiconductor could besilicon-germanium, germanium, or gallium arsenide.

Referring now to the drawings, where like elements are designated bylike reference numerals, FIGS. 1-13 illustrate a method of forming aDRAM memory device 100 (FIG. 13) having access transistors formedaccording to exemplary embodiments of the present invention. FIG. 1illustrates a semiconductor substrate 10 within which shallow trenchesisolation (STI) regions 20 have been formed by conventional methods. Inone exemplary embodiment, to obtain the shallow trenches isolationregions 20, the substrate 10 is first etched to a depth of about 100 nmto about 1,000 nm, preferably of about 300 nm. Subsequent to theformation of the shallow trenches, the trenches are filled with anisolation dielectric, for example, a high density plasma (HDP) oxide, amaterial which has a high ability to effectively fill narrow trenches.Alternatively, an insulating layer formed of an oxide or of siliconnitride, for example, may be formed on the trench sidewalls, prior tofilling the trenches with the isolation dielectric, to aid in smoothingout the corners in the bottom of the trenches and to reduce the amountof stress in the dielectric used to later fill in the trenches.

FIG. 1 also illustrates an insulating layer 14 formed over thesemiconductor substrate 10 according to conventional semiconductorprocessing techniques. Insulating layer 14 may comprise a silicon oxidesuch as a TEOS oxide or a nitride such as silicon nitride (Si₃N₄), forexample. The insulating layer 14 is formed over the substrate 10 to athickness of about 10 nm to about 1,000 nm, more preferably of about 200nm. Although reference to the insulating layer 14 will be made in thisapplication as to the TEOS oxide layer 14, it must be understood thatthe insulating layer 14 may be also formed of silicon nitride, forexample, or other insulating materials, and thus the invention is notlimited to the use of TEOS oxide. The TEOS oxide layer 14 may be formedby known deposition processes such as chemical vapor deposition (CVD) orlow temperature deposition by electron cyclotron resonance plasmaenhanced CVD, among others.

Next, the TEOS oxide layer 14 is patterned using a photoresist layer 15(FIG. 1) formed over the TEOS oxide layer 14 to a thickness of about 100nm to about 1,000 nm. The photoresist layer 15 is patterned with a mask(not shown) and the TEOS oxide layer 14 is anisotropically etchedthrough the patterned photoresist to obtain a plurality of TEOS oxidecolumns 18 or lines (FIG. 2) having a width W of about 50 nm to about100 nm, more preferably of about 80 nm, and a height H of about 20 nm toabout 800 nm, more preferably of about 200 nm. As shown in FIG. 2, theTEOS oxide columns 18 are spaced apart from each other by a distance D(illustratively about equal to the width W) of about 50 nm to about 100nm, more preferably of about 80 nm. As described in more detail below,the distance D represents the width of the portions of the self-alignedrecessed gate structures located above the surface of the substrate 10and formed according to embodiments of the present invention. The TEOSoxide columns 18 also define regions A adjacent and above surface 11 ofthe semiconductor substrate 10 and regions B adjacent and above thedielectric material of the STI regions 20, as shown in FIG. 2.

The photoresist layer 15 is removed by conventional techniques, such asoxygen plasma, for example, or by flooding the substrate 10 with UVirradiation to degrade the photoresist and obtain the structure of FIG.2.

Reference is now made to FIG. 3. Subsequent to the formation of the TEOSoxide columns 18, a thin sacrificial oxide layer 22 with a thickness ofabout 3 nm to about 20 nm, more preferably of about 5 nm, is thermallygrown over exposed surfaces 19 (FIG. 2) of the semiconductor substrate10 corresponding to regions A but not corresponding to regions B, asillustrated in FIG. 3. Since regions B are located over the fieldisolation oxide in regions 20, the oxide grown in the regions B isundetectable. As described in more detail below, the sacrificial oxidelayer 22 will be employed as an etch stop layer during a poly spaceretch. Subsequent to the formation of the sacrificial oxide layer 22, adoped or undoped polysilicon layer 24 is formed over the TEOS oxidecolumns 18, the thin sacrificial oxide layer 22 and the dielectricmaterial of the STI regions 20, as shown in FIG. 3. The polysiliconlayer 24 is formed to a thickness of about ¼ to ⅓ of the width W ordistance D (FIG. 2), by a deposition technique, for example CVD or LPCVDprocedures, at a temperature of about 300° C. to about 600° C.

The polysilicon layer 24 formed over the TEOS oxide columns 18, over thethin sacrificial oxide layer 22 and over the dielectric material of theSTI regions 20 is then partially etched with a first etchant, such as aselective etchant with HBr based chemistry, for example, that stops onthe sacrificial oxide layer 22 and on the dielectric material of the STIregions 20 and forms polysilicon spacers 25, 25 a, as shown in FIG. 4.The height of the polysilicon spacers 25, 25 a is adjustable byoveretching, depending on the desired depth of the recessed gate. Forexample, in one particular embodiment, the height of the polysiliconspacers 25, 25 a is of about 50 nm to about 500 nm, more preferably ofabout 100 nm.

Subsequent to the formation of the polysilicon spacers 25, 25 a of FIG.4, the semiconductor substrate 10 is etched by a directional etchingprocess with a second etchant having a high selectivity to oxide in aHBr ambient, for example, to a depth λ₁ (FIG. 5) of about 100 nm toabout 500 nm, more preferably of about 100 nm to about 150 nm, to obtainfirst transistor trenches or grooves 28 (FIGS. 5; 5 a) where a first setof recessed self-aligned gate structures of the DRAM memory device 100(FIG. 12) will be later formed as it will be described in detail below.At the end of the formation of the first transistor trenches 28, thepolysilicon spacers 25 are almost totally consumed, with polysiliconresidues 26 remaining adjacent the first transistor trenches 28, asshown in FIG. 5. The sacrificial oxide layer 22 under spacers 25 is notconsumed to protect the silicon surface from pitting caused by thesilicon-etch process. The first transistor grooves 28 are formed to awidth W₁ (FIG. 5) which is about ½ of the distance D of FIG. 2.

During the selective etch for the formation of the first transistortrenches 28, the dielectric material of the STI regions 20 is alsoetched to a depth 6 (FIG. 5) of about 1 nm to about 10 nm, morepreferably of about 5 nm. This etching of the dielectric materialdepends on etch selectivity of polysilicon etch with respect to oxide.The selective etching produces polysilicon residues 26 a (the same asresidues 26) and STI recesses 29 (FIG. 5) where a second set of recessedself-aligned gate structures of the DRAM memory device 100 (FIG. 12)will be later formed as it will be described in detail below.

Subsequent to the formation of the first transistor trenches 28 (FIGS.5; 5 a) and of the STI recesses 29 (FIG. 5), a third etch, for examplean isotropic etch or a wet etch such as a TMAH etch, is next conductedto remove polysilicon residues 26, 26 a remaining adjacent the firsttransistor trenches 28 and the STI recesses 29, respectively, and toobtain the structure of FIG. 6. As a result of the isotropic or wetetch, second transistor trenches or grooves 30 (FIGS. 6; 6 a) are alsoformed to a width W₂ which is greater than the width W₁ of the firsttransistor trenches 28, that is to a width W₂ which is up to ¾ thedistance D of FIG. 2. Second transistor grooves 30 are also formed to adepth λ₂ (FIG. 6), which is greater than the depth λ₁ of the firsttransistor grooves, that is to a depth λ₂ of about 200 nm to about 700nm, more preferably of about 250 nm to about 300 nm.

An optional cleaning step of all exposed surfaces of the semiconductorsubstrate 10 of FIG. 6 may be conducted at this step of processing.Alternatively, another sacrificial silicon oxide layer may be grown overthe exposed surfaces of the semiconductor substrate 10 of FIG. 6 andthen stripped by conventional methods to ensure removal of any existentimpurities, particulates and/or residue from the exposed surfaces, andto also smooth the silicon surface in the groove 30.

Subsequent to the formation of the second transistor trenches 30 and tothe optional cleaning step, a thin gate oxide layer 32 is selectivelyformed on the sidewalls and bottoms of the second transistor trenches 30and on the adjacent exposed surfaces of the semiconductor substrate 10corresponding to regions A but not over the recesses 29 corresponding toregions B, as shown in FIG. 7. The thin gate oxide layer 32 may bethermally grown in an oxygen ambient, at a temperature between about600° C. to about 1,000° C. and to a thickness of about 3 nm to about 10nm.

A polysilicon material 33 (FIG. 7) is then formed within both regions A,B as well as inside the second transistor trenches 30 and the STIrecesses 29 of the substrate 10. The polysilicon material 33 may be maybe doped n+ or p+ and may be blanket deposited over the structure ofFIG. 7, via LPCVD procedures at a temperature of about 300° C. to about600° C., for example, to completely fill regions A and B. Once regions Aand B are completely filled, the polysilicon material 33 is subjected toa mild isotropic poly etch to etch back parts of the polysilicon fromregions A and B and to form polysilicon gate layers 35 corresponding toregions A and to second transistor trenches 30, and polysilicon gatelayers 36 corresponding to regions B and to STI recesses 29, as shown inFIG. 8. The polysilicon gate layers 35, 36 extend above the surface 11of the semiconductor substrate 10 by a distance H₁ (FIG. 8) of about 5nm to about 100 nm, more preferably by about 25 nm. It must be notedthat the height H₁ of the polysilicon gate layers 35, 36 must be smallerthan the height H of the TEOS oxide columns 18, to allow the formationof the remaining metal-clad gate stack structures, as described indetail below.

Referring still to FIG. 8, a barrier layer 37 of about 5 nm to about 40nm is next formed over the polysilicon gate layers 35, 36. The barrierlayer 37 may be formed of tungsten nitride (WNx), titanium nitride (TiN)or titanium-rich TiN material, among others. Alternatively, the barrierlayer 37 may be a transition metal boride layer such as zirconium boride(ZrBx), titanium boride (TiBx), hafnium boride (HfBx) or tantalum boride(TaBx). Such materials exhibit good adhesion characteristics to siliconand, due to the low resistivities of about 5-150 microOhms-cm of thetransition metal borides, the total height of the gate stack can bedecreased.

Subsequent to the formation of the barrier layer 37, a conductivematerial 39 (FIG. 8) is formed, by blanket deposition for example, overthe barrier layer 37 and over the TEOS oxide columns 18, to completelycover the structure of FIG. 8. The conductive material 39 and thebarrier layer 37 are then subjected to a CMP process, for example, andsubsequently to an etching process to remove portions of the conductivematerial 39 and of the barrier layer 37 from the top of the TEOS oxidecolumns 18 and from in between the TEOS oxide columns 18, to form highlyconductive metal stacks 45, as shown in FIG. 9. Each of the highlyconductive stacks of FIG. 9 includes a patterned barrier layer 38 and aconductive layer 40. The conductive layer 40 can comprise a materialsuch as titanium (Ti) or titanium nitride (TiN), among others, orsimply, it can be formed by a silicide process such as cobalt silicide(CoSi), titanium silicide (TiSi), molybdenum silicide (MoSi) or nickelsilicide (NiSi), among others. As known in the art, TiSi and CoSi do notadhere well to gate dielectric materials and, as a consequence, they maylift from the gate dielectric materials; however, NiSi and MoSi areknown to adhere well to gate dielectric materials and they are fullysilicided when formed on an existing thin polysilicon film.

An insulating cap material of about 50 nm to about 100 nm is nextdeposited over substrate 10 to completely fill regions A and B of FIG. 8and the substrate top surface is planarized so that cap regions 55 (FIG.9) are formed over the highly conductive metal stacks 45. The capmaterial may be formed of silicon dielectrics such as silicon nitride orsilicon oxide, but TEOS, SOG (spin on glass) or carbides may be usedalso. The cap material may be also formed of an etch-stop insulatingmaterial.

Although the embodiments detailed above have been described withreference to the formation of a barrier layer, such as the transitionmetal boride layer 37, and of the conductive layer 40 formed over thetransition metal boride layer 37 to form highly conductive metal stacks45, it must be understood that the invention is not limited to theseembodiments. Accordingly, the present invention also contemplates theformation of other gate structures in lieu of the highly conductivemetal stacks 45. For example, and according to another embodiment of thepresent invention, a thin film of a transition metal such as titanium(Ti) or titanium nitride (TiN) having a thickness of less than 30 nm canbe deposited over the polysilicon gate layers 35, 36 by a PVD or CVDprocess. Optionally, the titanium or titanium nitride film can befurther exposed to a gas containing a dopant element such as boron, forexample. If boron is employed, the wafer is placed in a rapid thermalprocess (RTP) chamber and a flow of B₂H₆ or BF₃ gas diluted withhydrogen (H₂), nitrogen (N₂) and/or argon (Ar) gas is provided in thevicinity of the titanium or titanium nitride film to form the transitionmetal boride film.

In yet another embodiment, a thin film of a transition metal such astitanium (Ti) is deposited over the polysilicon gate layers 35, 36 andthen the polysilicon gate layers and the transition metal film aresubsequently implanted with a dopant such as boron. Accordingly, a dopedpolysilicon and the transition metal layer 37 can be formed by a singleboron implant.

Alternatively, a layer of metal capable of forming a silicide (notshown) such as cobalt, nickel, molybdenum, titanium or tungsten, forexample, may be deposited over the polysilicon gate layers 35, 36 to athickness of about 20 nm to about 50 nm. For deposition, sputtering byRF or DC may be employed but other similar methods such as CVD may beused. Subsequent to the deposition of the metal capable of forming asilicide, substrate 10 undergoes a rapid thermal anneal (RTA), typicallyfor about 10 to 60 seconds, using a nitrogen ambient, at about 600° C.to about 850° C. so that the metal in direct contact with thepolysilicon gate layers 35, 36 is converted to its silicide. Thesilicide regions form conductive regions on top of the polysilicon gatelayers 35, 36. Preferably, the refractory metal has low resistance andlow resistivity as a silicide. However, the refractory metal silicidemay comprise any refractory metal, including but not limiting totitanium, cobalt, tungsten, tantalum, molybdenum, nickel and platinum.If a silicide is employed, barrier layer 37 as described above may bealso optionally employed. The barrier layer 37 may be also omitted tosimplify the process steps. In any event, care must be taken later onduring the processing to prevent tungsten or silicide materials frombeing oxidized during the source/drain oxidation.

Reference is now made to FIG. 10. Subsequent to the formation of thehighly conductive metal stacks 45 and of the cap regions 55 (FIG. 9),the TEOS oxide columns 18 are removed by etching, for example, so thatthe formation of self-aligned recessed gate stacks 90, 190 (FIG. 10) ofDRAM memory device 100 is completed. Although the following processingsteps for the completion of the self-aligned recessed gate stacks 90,190 will refer to and illustrate the highly conductive metal stacks 45comprising conductive layer 40 formed over the patterned barrier layer38 and polysilicon gates layers 35, 36, it must be understood that thepresent invention is not limited to this embodiment, and otherembodiments such as the formation of gate stacks comprising a dielectricmaterial (for example, a high-k dielectric material) formed over thepolysilicon gates, for example, are also contemplated. Additionally,gate stacks comprising non-silicide materials such as TiN, WN, Ta, TaNor Nb, among others, which may be employed as direct gate materials ongate dielectrics, are also contemplated by the present invention, and itmust be understood that the above-described embodiments are onlyexemplary and the invention is not limited to them.

At this point self-aligned recessed gate stacks 90 (FIG. 10) (eachhaving gate oxide layer 32, polysilicon gate layer 35, highly conductivemetal stack 45 and nitride cap 55) and self-aligned recessed gate stacks190 (FIG. 10) (each having polysilicon gate layers 36, highly conductivemetal stack 45 and nitride cap 55) have been formed. The self-alignedrecessed gate stacks 90, 190 may now be used in a conventional iniplantprocess where the gate structures are used as masks for the dopantimplantation of source and drain regions as further described below.

At this point, processing steps for transistor formation proceedaccording to conventional semiconductor processing techniques. The nextstep in the flow process is the growth of a selective oxide 94 (FIG. 11)on the exposed surfaces of the semiconductor substrate 10 obtained as aresult of the removal of the TEOS oxide columns 18 (FIG. 9), as well ason the polysilicon sidewalls of the gate stacks 90, 190. The selectiveoxide 94 may be thermally grown in an oxygen and hydrogen ambient, at atemperature between about 600° C. to about 1,000° C. and to a thicknessof about 3 nm to about 8 nm. Subsequent to the formation of theselective oxide 94, a layer 95 of spacer dielectric material, such asnitride material for example, is formed over the gate stacks 90, 190 andthe selective oxide 94, as shown in FIG. 11.

The self-aligned recessed gate stacks 90, 190 protected by layer 95 ofnitride material and by the selective oxide 94 can now undergoconventional processing steps for the formation of source and drainregions 92, 96 and of lightly doped drain (LDD) regions 96 a, as shownin FIG. 12. For this, doping through layer 95 and the selective oxide 94is conducted to form the source and drain regions 92, 96 and the lightlydoped drain (LDD) regions 96 a, subsequently to which layer 95 andselective oxide 94 are etched back to form nitride spacers 95 a, alsoillustrated in FIG. 12. Alternatively, the layer 95 of nitride materialand the selective oxide 94 are first etched back to form nitride spacers95 a, and then the resulting structure is subjected to doping for theformation of the source and drain regions 92, 96 and the lightly dopeddrain (LDD) regions 96 a.

Subsequent to the formation of the source and drain regions 92, 96 andthe lightly doped drain (LDD) regions 96 a of FIG. 12, contact openingsfor conductors 117 and/or capacitors 107 into semiconductor substrate 10through an oxide layer 110 such as BPSG, for example, are also formed toproduce a semiconductor device such as the DRAM memory device 100, allillustrated in FIG. 13. Although, for simplicity, FIG. 13 illustratesthe formation of bit line 118 over the capacitor structures 107, it mustbe understood that this embodiment is only exemplary and the inventionalso contemplates the formation of a bit line under capacitor (orcapacitor over bit line (COB)). In fact, an embodiment with a COB isdesirable as it would decrease the length of the plug to silicon which,in turn, would decrease the parasitic capacity of the bit line.

The self-aligned recessed gate stacks 90, 190 (FIGS. 10-13) andassociated transistors formed in accordance with embodiments of thepresent invention could be used in any integrated circuit structure. Inone example, they can be used in a processor-based system 400 whichincludes a memory circuit 448, for example the DRAM memory device 100,as illustrated in FIG. 14. A processor system, such as a computersystem, generally comprises a central processing unit (CPU) 444, such asa microprocessor, a digital signal processor, or other programmabledigital logic devices, which communicates with an input/output (I/O)device 446 over a bus 452. The memory 448 communicates with the systemover bus 452.

Although the embodiments of the present invention have been describedabove with reference to the formation of self-aligned recessed gatestacks 90, 190 comprising specific materials, such as the polysiliconmaterial for the formation of layers 35, 36 for example, it must beunderstood that the present invention is not limited to these specificexamples. Accordingly, the present application has applicability toother gate metals or materials known in the art, or combination of suchmetals and materials, for the formation of the self-aligned recessedgate stacks 90, 190 of the present invention.

In addition, although the embodiments of the present invention have beendescribed above with reference to the formation of polysilicon spacers,such as the polysilicon spacers 25, 25 a, over a thin oxide layer, suchas the thin sacrificial oxide layer 22, and over TEOS oxide columns,such as TEOS oxide columns 18, it must be understood that the presentinvention is not limited to these three specific materials. Accordingly,the present application has applicability to other materials, orcombination of such materials, for the formation of the spacers, of theoxide layer and of the columns used for the formation of theself-aligned recessed gate stacks 90, 190. For example, the presentinvention also contemplates using a high-k dielectric material, HfO₂, orAl₂O₃/ZrO₂ among others, in addition to the conventional oxide andnitride materials. Thus, the polysilicon/oxide/TEOS oxide combination(corresponding to the polysilicon spacers/thin oxide layer/TEOS oxidecolumns) is only one exemplary embodiment of the present invention.

The above description and drawings are only to be consideredillustrative of exemplary embodiments which achieve the features andadvantages of the present invention. Modification and substitutions tospecific process conditions and structures can be made without departingfrom the spirit and scope of the present invention. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

1-99. (canceled)
 100. A method of forming a recessed gate structure, comprising the acts of: forming insulating columns over a semiconductor substrate; forming at least a trench within said semiconductor substrate and adjacent said insulating columns; forming a gate oxide on the bottom and sidewalls of said trench; and forming a conductive region at least partially within said trench.
 101. The method of claim 100, wherein said insulating columns are spaced apart from each other by a distance of about 50 nm to about 100 nm.
 102. The method of claim 100, wherein said insulating columns are formed to a height of about 20 nm to about 800 nm.
 103. The method of claim 100, wherein said trench is etched to a depth of about 200 nm to about 700 nm.
 104. The method of claim 103, wherein said trench is formed to a width of less than about 75% of said distance.
 105. The method of claim 100, wherein said conductive region comprises polysilicon.
 106. The method of claim 100, wherein said conductive region comprises a metal.
 107. The method of claim 100, wherein said conductive region comprises a silicide.
 108. A method of forming a transistor structure, the method comprising the acts of: providing at least one shallow trench isolation region within a substrate; forming a first conductive region at least partially within said shallow trench isolation region; forming a second conductive region above said first conductive region and electrically connected to said first conductive region; and forming source and drain regions within said semiconductor substrate on sides of said first conductive region.
 109. The method of claim 108 further comprising the step of providing insulating spacers on sidewalls of said first conductive region but not on sidewalls of said second conductive region.
 110. The method of claim 108, wherein said shallow trench isolation region has a depth of about 200 nm to about 700 nm.
 111. The method of claim 108, wherein said first conductive region and said second conductive region independently comprise polysilicon or a metal.
 112. The method of claim 108, wherein said first and said second conductive regions comprise a metal silicide.
 113. A method of forming at least two self-aligned gate structures for a semiconductor device, the method comprising the acts of: providing a shallow trench isolation region within a semiconductor substrate; providing a trench structure within said semiconductor substrate and laterally displaced from said shallow trench isolation region; and simultaneously forming a first self-aligned gate structure at least partially within said shallow trench isolation region and a second self-aligned gate structure within and above said trench structure.
 114. The method of claim 113 further comprising the acts of: forming a plurality of insulating columns spaced apart from each other and to expose regions of said semiconductor substrate; providing an oxide layer over said regions of said semiconductor substrate; providing a dielectric material on sidewalls of each of said plurality of insulating columns and over portions of said oxide layer; and defining said trench structure in said semiconductor substrate and extending through said oxide layer.
 115. The method of claim 114, wherein said act of providing said first self-aligned gate structure further comprises the act of forming a polysilicon layer to partially fill said shallow trench isolation region.
 116. The method of claim 114, wherein said act of providing said second self-aligned gate structure further comprises the act of forming a polysilicon layer to completely fill said trench structure.
 117. The method of claim 114 further comprising the acts of: forming a first conductive region of said first self-aligned gate structure and a second conductive region of said second self-aligned gate structure; forming a transition metal layer over each of said first and second conductive regions and in between said adjacent insulating columns; forming a cap layer over said transition metal layer and in between adjacent insulating columns; and removing said insulating columns. 